High-speed counter or pulse output: control code setting
The data register stores the control code.
FP0, FP-e
The 16 bits of the data register are allocated in groups of four to high-speed counter channels 0–3. Applicable channel numbers are indicated in parentheses:
- Bit 0 (0), 4 (1), 8 (2), 12 (3) =0/1: Software reset ® no/yes
- Bit 1 (0), 5 (1), 9 (2), 13 (3) =0/1: Counting ® enable/disable
- Bit 2 (0), 6 (1), 10 (2), 14 (3) =
- 0/1: Hardware reset ® enabled/disabled (high-speed counter)
- 0/1: Near home input ® off/on (pulse output)
- Bit 3 (0), 7 (1), 11 (2), 15 (3) =
- 0/1: High-speed counter instruction ® continue/stop (high-speed counter)
- 0/1: Pulse output ® continue/stop (pulse output)
FP
S
The control code settings for each channel can be monitored using the system variables sys_wHscChannelxControlCode or sys_wPulseChannelxControlCode (where x=channel number).
- Bit 0 = 0/1: Software reset ® no/yes
- Bit 1 = 0/1: Counting ® enable/disable
- Bit 2 = 0/1: Hardware reset ® enabled/disabled (high-speed counter)
- Bit 3 = 0/1: High-speed counter instruction ® continue/stop (high-speed counter)
- Bit 3 = 0/1: Pulse output ® continue/stop (pulse output)
- Bit 4 = 0/1: Near home input ® off/on (pulse output)
- Bit 12–15: Channel number 16#n
FP-X
The control code settings for each channel can be monitored using the system variables sys_wHscChannelxControlCode or sys_wPulseChannelxControlCode (where x=channel number).
- Bit 0 = 0/1: Software reset ® no/yes
- Bit 1 = 0/1: Counting ® enable/disable
- Bit 2 = 0/1: Hardware reset ® enabled/disabled (high-speed counter)
- Bit 3 = 0/1: High-speed counter instruction ® continue/stop (high-speed counter)
- Bit 3 = 0/1: Pulse output ® continue/stop (pulse output)
- Bit 4 = 0/1: Near home input ® off/on (pulse output)
- Bit 8 = 0/1: High-speed counter/pulse output
- Bit 12–15: Channel number 16#n
