The default initial values are 0 or FALSE.
Availability of memory areas:
The FP series PLCs have many different memory areas, which support 1-bit, 16-bit, or 32-bit addressing. Availability of the memory areas varies, depending on the PLC's processor. Addresses may be specified in FP format (e.g. X) or IEC format (%IX).
Memory area |
1-bit |
16-bit |
32-bit |
64-bit |
16-bit PLCs |
32-bit PLCs |
---|---|---|---|---|---|---|
Input |
X |
WX |
DWX |
● |
||
LWX2) |
● |
|||||
Output |
Y |
WY |
DWY |
● |
||
LWY2) |
● |
|||||
Internal flag |
R |
WR |
DWR |
● |
||
LWR2) |
● |
|||||
Timer flag |
T |
● |
●1) |
|||
Timer set value register |
SV |
● |
||||
TSV |
●1) |
|||||
Timer elapsed value register |
EV |
● |
||||
TEV |
●1) |
|||||
Counter flag |
C |
● |
●1) |
|||
Counter set value register |
SV |
● |
||||
CSV |
●1) |
|||||
Counter elapsed value register |
EV |
● |
||||
CEV |
● |
|||||
Data register |
DT |
DDT |
● |
● |
||
LDT2) |
● |
|||||
File register |
FL |
DFL |
● |
|||
Link flag |
L |
WL |
DWL |
● |
● |
|
LWL2) |
● |
|||||
Link register |
LD |
DLD |
● |
● |
||
LLD2) |
● |
|||||
System flag |
SR |
WSR |
DWS |
● |
||
System data |
SD |
● |
||||
DSD |
||||||
Unit memory |
Sx:UM |
Sx:DUM |
● |
|||
Index register |
IX |
● |
||||
DIX |
● |
|||||
Error alarm flag |
E |
● |
● |
|||
Pulse flag |
P |
● |
1) On the FP7, these addresses are reserved for the system.
2) Supported for data type LREAL on 32-bit PLCs only.